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U.S., ARMENIAN INVENTORS DEVELOP MEMORIES SELF TESTING METHOD
US Fed News
November 5, 2007 Monday 5:32 AM EST
ALEXANDRIA, Va., Nov. 5 -- Gevorg Torjyan and Albert Harutyunyan,
both of Yerevan, Armenia, Yervant Zorian of Santa Clara, Calif.,
and Karen Darbinyan of Fremont, Calif., have developed a memories
self testing method.
An abstract of the invention, released by the U.S. Patent & Trademark
Office, said: "Methods and apparatuses in which two or more memories
share a processor for Built In Self Test algorithms and features
are described. The processor initiates a Built In Self Test for
the memories. Each memory has an intelligence wrapper bounding that
memory. Each intelligence wrapper contains control logic to decode a
command from the processor. Each intelligence wrapper contains logic
to execute a set of test vectors on a bounded memory. The processor
sends a command based self-test to each intelligence wrapper at a first
clock speed and the control logic executes the operations associated
with that command at a second clock speed asynchronous with the first
speed. The processor loads the command containing representations of
a march element and data to one or more of the intelligence wrappers
via a serial bus."
The inventors were issued U.S. Patent No. 7,290,186 on Oct. 30.
The patent has been assigned to Virage Logic Corp., Fremont.
The original application was filed on
Sept. 16, 2003, and is available at:
http://patft.uspto.gov/netacgi/nph-Parser?Sect 1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=% 2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G& ;l=50&s1=7,290,186.PN.&OS=PN/7,290,186& ;RS=PN/7,290,186.
For more information about US Fed News federal patent awards please
contact: Myron Struck, Managing Editor/US Bureau, US Fed News, Direct:
703/866-4708, Cell: 703/304-1897, [email protected]
US Fed News
November 5, 2007 Monday 5:32 AM EST
ALEXANDRIA, Va., Nov. 5 -- Gevorg Torjyan and Albert Harutyunyan,
both of Yerevan, Armenia, Yervant Zorian of Santa Clara, Calif.,
and Karen Darbinyan of Fremont, Calif., have developed a memories
self testing method.
An abstract of the invention, released by the U.S. Patent & Trademark
Office, said: "Methods and apparatuses in which two or more memories
share a processor for Built In Self Test algorithms and features
are described. The processor initiates a Built In Self Test for
the memories. Each memory has an intelligence wrapper bounding that
memory. Each intelligence wrapper contains control logic to decode a
command from the processor. Each intelligence wrapper contains logic
to execute a set of test vectors on a bounded memory. The processor
sends a command based self-test to each intelligence wrapper at a first
clock speed and the control logic executes the operations associated
with that command at a second clock speed asynchronous with the first
speed. The processor loads the command containing representations of
a march element and data to one or more of the intelligence wrappers
via a serial bus."
The inventors were issued U.S. Patent No. 7,290,186 on Oct. 30.
The patent has been assigned to Virage Logic Corp., Fremont.
The original application was filed on
Sept. 16, 2003, and is available at:
http://patft.uspto.gov/netacgi/nph-Parser?Sect 1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=% 2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G& ;l=50&s1=7,290,186.PN.&OS=PN/7,290,186& ;RS=PN/7,290,186.
For more information about US Fed News federal patent awards please
contact: Myron Struck, Managing Editor/US Bureau, US Fed News, Direct:
703/866-4708, Cell: 703/304-1897, [email protected]